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this is information on a product in full production. april 2014 docid024671 rev 2 1/15 15 STL40N10F7 n-channel 100 v, 0.02 typ., 10 a, stripfet? vii deepgate? power mosfet in a powerflat? 5x6 package datasheet ? production data figure 1. internal schematic diagram features ? ultra low on-resistance ? 100% avalanche tested applications ? switching applications description this device is an n-channel power mosfet developed using the 7 th generation of stripfet? deepgate? technology, with a new gate structure. the resulting power mosfet exhibits the lowest r ds(on) in all packages. $0y ' * 6 powerflat? 5x6 1 2 3 4 order code v ds r ds(on) max i d p tot STL40N10F7 100 v 0.024 10 a 5 w table 1. device summary order code marking package packaging STL40N10F7 40n10f7 powerflat? 5x6 tape and reel www.st.com
contents STL40N10F7 2/15 docid024671 rev 2 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
docid024671 rev 2 3/15 STL40N10F7 electrical ratings 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 100 v v gs gate-source voltage 20 v i d (1) 1. this value is rated according to r thj-c. drain current (continuous) at t c = 25 c 40 a i d (1) drain current (continuous) at t c = 100 c 28 a i d (2) 2. this value is rated according to r thj-pcb. drain current (continuous) at t pcb = 25 c 10 a i d (2) drain current (continuous) at t pcb =100 c 7 a i dm (2)(3) 3. pulse width limited by safe operating area. drain current (pulsed) 40 a p tot (1) total dissipation at t c = 25 c 70 w p tot (2) total dissipation at t pcb = 25 c 5 w t j t stg operating junction temperature storage temperature -55 to 175 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 2.08 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1 inch2, 2oz cu, t < 10 sec thermal resistance junction-pcb max 31 c/w
electrical characteristics STL40N10F7 4/15 docid024671 rev 2 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage v gs = 0, i d = 250 a 100 v i dss zero gate voltage drain current v gs = 0, v ds = 100 v 10 a v gs = 0, v ds = 100 v, t c =125 c 100 a i gss gate-body leakage current v ds = 0, v gs = +20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a2.5 4.5v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 10 a 0.02 0.024 table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 50 v, f = 1 mhz, v gs = 0 - 1270 - pf c oss output capacitance - 290 - pf c rss reverse transfer capacitance -24-pf q g total gate charge v dd = 50 v, i d = 32 a, v gs = 10 v (see figure 14 ) -19-nc q gs gate-source charge - 9 - nc q gd gate-drain charge - 4.5 - nc table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 50 v, i d = 16 a, r g = 4.7 , v gs = 10 v (see figure 13 ) -12-ns t r rise time - 17.5 - ns t d(off) turn-off delay time - 22 - ns t f fall time - 5.6 - ns
docid024671 rev 2 5/15 STL40N10F7 electrical characteristics table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current - - 32 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - - 128 a v sd (2) 2. pulsed: pulse duration = 300 s, duty cycle 1.5%. forward on voltage i sd = 32 a, v gs = 0 - - 1.1 v t rr reverse recovery time i sd = 32 a, di/dt = 100 a/ s v dd = 80 v, t j =150 c -41 ns q rr reverse recovery charge - 47 nc i rrm reverse recovery current - 2.3 a
electrical characteristics STL40N10F7 6/15 docid024671 rev 2 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance i d 10 1 0.1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10ms 1s 100ms 0.01 tj=175c tpcb=25c single pulse gipg270320141147sa single pulse =0.5 0.05 0.02 0.01 0.1 0.2 k 10 t p (s) -4 10 -3 10 -2 10 -1 10 -5 10 -3 10 -2 10 -1 10 0 pcb 10 1 gipg270320141356sa i d 100 60 20 0 0 2 v ds (v) 4 (a) 6 5v 6v v gs =10v 40 80 7v 8v 9v 8 am16174v1 i d 80 40 0 0 4 v gs (v) 8 (a) 2 6 10 20 60 100 v ds =10v am16175v1 v gs 6 4 2 0 0 10 q g (nc) (v) 8 15 20 10 v dd =50v i d =32a 12 5 am16176v1 r ds(on) 19.00 18.50 18.00 0 20 i d (a) (m ) 10 30 19.50 v gs =10v 20.00 20.50 21.00 21.50 am16177v1
docid024671 rev 2 7/15 STL40N10F7 electrical characteristics figure 8. capacitance variations figure 9. normalized gate threshold voltage vs temperature figure 10. normalized on-resistance vs temperature figure 11. normalized v (br)dss vs temperature figure 12. source-drain diode forward characteristics c 1200 400 200 0 0 20 v ds (v) (pf) 10 30 ciss coss crss 40 50 60 70 80 600 800 1000 1400 am16178v1 v gs(th) 0.6 0.4 0.2 0 -55 -5 t j (c) (norm) -30 0.8 70 20 45 95 i d =250a 120 1 1.2 145 am16179v1 r ds(on) 2 1 0 t j (c) (norm) 0.5 1.5 -55 -5 -30 70 20 45 95 120 v gs =10v am16180v1 v (br)dss t j (c) (norm) 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 i d =250 a 1.04 -55 -5 -30 70 20 45 95 120 am16181v1 v sd 0 10 i sd (a) (v) 5 25 15 20 0.5 0.6 0.7 0.8 t j =-55c t j =150c t j =25c 0.9 1 30 am16182v1
test circuits STL40N10F7 8/15 docid024671 rev 2 3 test circuits figure 13. switching times test circuit for resistive load figure 14. gate charge test circuit figure 15. test circuit for inductive load switching and diode recovery times figure 16. unclamped inductive load test circuit figure 17. unclamped inductive waveform figure 18. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
docid024671 rev 2 9/15 STL40N10F7 package mechanical data 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data STL40N10F7 10/15 docid024671 rev 2 figure 19. powerflat? 5x6 type s-r drawing 5 8 4 1 pin 1 identification 1 4 5 8 pin 1 identification . side view top view bottom view 8231817_rev.h_type s-r
docid024671 rev 2 11/15 STL40N10F7 package mechanical data figure 20. recommended footprint table 8. powerflat 5x6 type s-r mechanical data dim. mm min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 5.95 6.15 6.35 d2 4.11 4.31 e2 3.50 3.70 e1.27 l 0.60 0.80 k 1.275 1.575 footprint
packaging mechanical data STL40N10F7 12/15 docid024671 rev 2 5 packaging mechanical data figure 21. powerflat? 5x6 tape (a) figure 22. powerflat? 5x6 package orientation in carrier tape a. all dimensions are in millimeters. measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c pin 1 identification
docid024671 rev 2 13/15 STL40N10F7 packaging mechanical data figure 23. powerflat? 5x6 reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo at t e n t i o n observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
revision history STL40N10F7 14/15 docid024671 rev 2 6 revision history table 9. document revision history date revision changes 20-may-2013 1 first release. 02-apr-2014 2 ? document status promoted from preliminary data to production data ? modified: v gs(th) values in table 4 ? modified: the entire typical values in table 5 , 6 and 7 ? added: section 2.1: electrical characteristics (curves) ? updated: figure 13 , 14 , 15 and 16 ? minor text changes
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